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1 features ? low-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) internally organized 131,072 x 8 2-wire serial interface schmitt triggers, filtered inputs for noise suppression bi-directional data transfer protocol 400 khz (2.7v) and 1 mhz (5v) clock rate write protect pin for hardware and software data protection 256-byte page write mode (partial page writes allowed) random and sequential read modes self-timed write cycle (5 ms typical) high reliability ? endurance: 100,000 write cycles/page ? data retention: 40 years 8-lead pdip, 8-lead eiaj soic, 8-lead lap and 8-ball dbga tm packages description the at24C1024 provides 1,048,576 bits of seri al electrically erasable and program- mable read only memory (eeprom) organized as 131,072 words of 8 bits each. the device?s cascadable feature allows up to 2 devices to share a common 2-wire bus. the device is optimized for use in many industrial and commercial applications where low- power and low-voltage operation are essential. the devices are available in space- saving 8-lead pdip, 8-lead eiaj soic, 8-lead leadless array (lap) and 8-ball dbga packages. in addition, the entire family is available in 2.7v (2.7v to 5.5v) versions. 2-wire serial eeprom 1m (131,072 x 8) at24C1024 rev. 1471h?seepr?03/03 pin configurations pin name function a1 address input sda serial data scl serial clock input wp write protect nc no connect 8-lead pdip 1 2 3 4 8 7 6 5 nc a1 nc gnd vcc wp scl sda 8-lead leadless array bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda nc a1 nc gnd 8-lead soic 1 2 3 4 8 7 6 5 nc a1 nc gnd vcc wp scl sda 8-ball dbga bottom view vcc wp scl sda nc a1 nc gnd 1 2 3 4 8 7 6 5
2 at24C1024 1471h?seepr?03/03 block diagram absolute maximum ratings* operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24C1024 1471h?seepr?03/03 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bi-directional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open-collector devices. device/page addresses (a1): the a1 pin is a device address input that can be hard- wired or left not connected for hardware compatibility with at24c128/256/512. when the a1 pin is hardwired, as many as two 1024k dev ices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). when the pin is not hardwired, the default a1 is zero. write protect (wp): the hardware write protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. the write-protect input, when tied to gnd, allows normal write operations. when wp is tied high to v cc , all write operations to the memory are inhibited. if left unconnected, wp is internally pulled down to gnd. switching wp to v cc prior to a write operation creates a software write-protect function. memory organization at24C1024, 1024k serial eeprom: the 1024k is internally organized as 512 pages of 256 bytes each. random word addressing requires a 17-bit data word address.
4 at24C1024 1471h?seepr?03/03 pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +2.7v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +2.7v to +5.5v, t ac = 0 c to +70 c, v cc = +2.7v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 2.7 5.5 v i cc supply current v cc = 5.0v read at 400 khz 2.0 ma i cc supply current v cc = 5.0v write at 400 khz 5.0 ma i sb standby current v cc = 2.7v v in = v cc or v ss 3.0 a v cc = 5.5v 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) -0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol output low level v cc = 3.0v i ol = 2.1 ma 0.4 v
5 at24C1024 1471h?seepr?03/03 ac characteristics notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.7v, 5v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc applicable over recommended operating range from t a = -40 c to +85 c, v cc = +2.7v to +5.5v, c l = 100 pf (unless otherwise noted). test conditions are listed in note 2. symbol parameter test conditions min max units f scl clock frequency, scl 4.5v v cc 5.5v 2.7v v cc 5.5v 1000 400 khz t low clock pulse width low 4.5v v cc 5.5v 2.7v v cc 5.5v 0.4 1.3 s t high clock pulse width high 4.5v v cc 5.5v 2.7v v cc 5.5v 0.4 0.6 s t aa clock low to data out valid 4.5v v cc 5.5v 2.7v v cc 5.5v 0.05 0.05 0.55 0.9 s t buf time the bus must be free before a new transmission can start (1) 4.5v v cc 5.5v 2.7v v cc 5.5v 0.5 1.3 s t hd.sta start hold time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t su.sta start setup time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t hd.dat data in hold time 0 s t su.dat data in setup time 100 ns t r inputs rise time (1) 0.3 s t f inputs fall time (1) 4.5v v cc 5.5v 2.7v v cc 5.5v 100 300 ns t su.sto stop setup time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t dh data out hold time 50 ns t wr write cycle time 10 ms endurance (1) 5.0v, 25 c, page mode 100k write cycles
6 at24C1024 1471h?seepr?03/03 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only dur ing scl low time periods (refer to data validity timing diagram). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to start and stop definition timing diagram). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowl- edge that it has received each word. standby mode: the at24C1024 features a low-power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: 1. clock up to 9 cycles, 2. look for sda high in each cycle while scl is high. 3. create a start condition.
7 at24C1024 1471h?seepr?03/03 bus timing (scl: serial cloc k, sda: serial data i/o) write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. (1)
8 at24C1024 1471h?seepr?03/03 data validity start and stop definition output acknowledge
9 at24C1024 1471h?seepr?03/03 device addressing the 1024k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to figure 1). the device address word con- sists of a mandatory one, zero sequence for the first five most significant bits as shown. this is common to all 2-wire eeprom devices. the 1024k uses the one device address bit, a1, to allow up to two devices on the same bus. the a1 bit must compare to the corresponding hardwired input pin. the a1 pin uses an inter- nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float. the seventh bit (p 0 ) of the device address is a memory page address bit. this memory page address bit is the most significant bit of the data word address that follows. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the e eprom will output a zero. if a compare is not made, the device will return to a standby state. data security: the at24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the wp pin is at v cc . write operations byte write: to select a data word in the 1024k memory requires a 17-bit word address. the word address field consists of the p 0 bit of the device address, then the most significant word address followed by the least significant word address (refer to figure 2) a write operation requires the p 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero. the addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (refer to figure 2). pag e wr it e : the 1024k eeprom is capable of 256-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must ter- minate the page write sequence with a stop condition (refer to figure 3). the data word address lower 8 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 256 data words are transmitted to the eeprom, the data word addre ss will ?roll over? and previous data will be overwritten. the address ?rollover? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero, allowing the read or write sequence to continue.
10 at24C1024 1471h?seepr?03/03 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?rollover? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write sele ct bit set to one is clocked in and acknowl- edged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condi- tion (refer to figure 4). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a fol- lowing stop condition (refer to figure 5). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (refer to figure 6).
11 at24C1024 1471h?seepr?03/03 figure 1. device address figure 2. byte write figure 3. page write figure 4. current address read 0 significant most significant least p 0 p 0 significant most significant least
12 at24C1024 1471h?seepr?03/03 figure 5. random read figure 6. sequential read p 0 p 0
13 at24C1024 1471h?seepr?03/03 note: for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics table s. ordering information ordering code package operation range at24C1024-10ci-2.7 at24C1024c1-10ci-2.7 at24C1024-10pi-2.7 at24C1024w-10si-2.7 at24C1024-10ui-2.7 8cn3 8cn1 8p3 8s2 8u8 industrial (-40 c to 85 c) package type 8cn3 8-lead, 0.230" wide, leadless array package (lap) 8cn1 8-lead, 0.300" wide, leadless array package (lap) 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u8 8-ball, die ball grid array package (dbga) options -2.7 low voltage (2.7v to 5.5v)
14 at24C1024 1471h?seepr?03/03 packaging information 8cn3 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn3 , 8-lead, (6 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn3 11/14/01 pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 5.89 5.99 6.09 e 4.83 4.93 5.03 e 1.27 bsc e1 0.56 ref l 0.62 0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions.
15 at24C1024 1471h?seepr?03/03 8cn1 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn1 , 8-lead (8 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn1 11/13/01 pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 7.90 8.00 8.10 e 4.90 5.00 5.10 e 1.27 bsc e1 0.60 ref l 0.62 0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions.
16 at24C1024 1471h?seepr?03/03 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
17 at24C1024 1471h?seepr?03/03 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 5/2/02 8s2 b top view side view end view h 1 n c e a b l a1 e d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm . a 1.78 2.03 a1 0.05 0.33 b 0.35 0.51 5 c 0.18 0.25 5 d 5.13 5.38 e 5.13 5.41 2, 3 h 7.62 8.38 l 0.51 0.89 e 1.27 bsc 4
18 at24C1024 1471h?seepr?03/03 8u8 ? dbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8u8 , 8-ball 0.75 pitch, die ball grid array package (dbga) at24C1024 (at35520) 01/09/02 8u8 a d e bottom view side view top view d e a2 a 4 3 2 1 8 7 6 5 e1 d1 a1 - z - z m 8 0 . 0 y x z m 5 1 . 0 ?b # # # # pin 1 mark this corner common dimensions (unit of measure = mm) symbol min nom max note d 3.84 d1 0.80 typ e 2.85 e1 1.05 typ e 0.75 typ d 0.75 typ a 0.90 ref a1 0.49 0.52 0.55 a2 0.35 0.38 0.41 ? b 0.47 0.50 0.53 notes: 1. this drawing is for general information only. no jedec drawing to refer to for additional information. 2. dimension is measured at the maximum solder ball diameter, parallel to primary datum z.
printed on recycled paper. 1471h?seepr?03/03 xm disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof, are the registered trademarks, and dbga ? is the trademark of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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